1. Field of the Invention
The present invention relates to a semiconductor package and method of manufacturing the same.
2. Description of the Related Art
FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package. As shown in FIG. 1, the semiconductor package 100 has a semiconductor device 102 flip-chip bonded (for example, through a plurality of solder balls 108) to a substrate 104. An underfill layer 106 is formed in the space between the semiconductor device 102 and the substrate 104 to increase the mechanical strength of the bondage between the semiconductor device 102 and the substrate 104, and fix their positions relative to each other. Hence, the semiconductor package 100 is prevented from possible dissociation or deformation when it is subjected to a surface bonding process.
However, moisture buried within the underfill layer 106 and volatile pollutants trapped on the surface of the semiconductor device 102 and the substrate 104 may vaporize and expand when it is subjected to heat. As a result, voids are produced in the underfill layer 106. These voids may cause the delamination of the underfill layer 106 from the semiconductor device 102 or substrate 104. Moreover, the heat-produced moisture or pollutants are still enclosed by the underfill layer 106 under thermal vaporization, incapable of dissipating away. Hence, the moisture and pollutants may condense on the solder balls 108 when the temperature drops leading to the possible formation of a conductive bridge between neighboring solder balls 108. In general, the gap between the semiconductor device 102 and the substrate 104 is relatively small so that it is very difficult to have a controlled injection of underfill material into the space, and the problem of effusion occurs often.